A conventional bipolar semiconductor differential amplifier includes a matched pair of loads (active or passive) connected between the collector electrodes of a pair of emitter coupled transistors and the supply voltage. A current source is connected between the common emitters of the pair of transistors and ground reference. Input signals are applied to the base electrodes of the pair of transistors, and output signals are taken from the collector electrodes. In a semiconductor memory system, the inputs originate from signals that occur on bit lines of an array of memory cells.
During operation, when the emitter current source is enabled, the differential input signals cause one transistor of the pair to increase conduction and the other to decrease conduction. As a detector in a digital system, such as a semiconductor memory system, the conducting transistor conducts all of the emitter current and the other is cutoff.
It is desirable to design the differential amplifier to operate very fast, i.e., to switch states very rapidly. Input differential signals are applied through a D.C. voltage shifter to the gate electrodes of the pair of transistors of the differential amplifier. In an effort to speed up operation, designers have increased the gain of the circuit by increasing the load, e.g., by increasing the value of the load resistance. Gain is proportional to the value of the load. The increased load causes large voltage swings at the collector output terminals and can cause the amplifier circuit to go into saturation. If the amplifier circuit goes into saturation, it slows down and also may latch-up.
To avoid excessive collector voltage swings, the collector electrodes have been clamped by diode connected transistors positioned across the loads of the differential pair of transistors. If a single diode connected transistor is used on each side of the differential pair, the swing of the collector voltage is limited to a single diode voltage drop. If two diode-connected transistors are connected in series across the load on each side of the differential amplifier, the swing of the collector voltage is limited to two diode voltage drops. By thus clamping the collector voltage, the differential amplifier output signal swings are a fixed value for large loads. Since clamping is determined by the supply voltage that is local to the collectors of the differential amplifier, there is no clamp voltage tacking of the variations in either the D.C. voltage level or the A.C. signal strength of the input differential signal that is applied to the base electrodes of the differential amplifier. To safeguard against this drawback, one has to either severely limit the gain of the differential amplifier by using small loads and slow speed or run the risk of forward-biasing the base to collector junctions of the transistors of the differential amplifier and possible latch-up.
The problem is to design a differential amplifier circuit that operates very fast with either a high voltage or a low voltage collector supply. The circuit should not be slow when installed with a low voltage supply nor driven into saturation or caused to latch-up when installed with a high voltage supply.
This problem is not unique to a differential amplifier. A single-ended input/output amplifier is confronted by the same problem.